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| PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. Separate Terminal Count Up and Terminal Count Down outputs are provided which are used as the clocks for a subsequent stages without extra logic, thus simplifying multistage counter designs. Individual preset inputs allow the circuits to be used as programmable counters. Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks. SN54/74LS192 SN54/74LS193 PRESETTABLE BCD / DECADE UP/ DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/ DOWN COUNTER LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 16 1 * * * * * * * Low Power . . . 95 mW Typical Dissipation High Speed . . . 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects 16 1 N SUFFIX PLASTIC CASE 648-08 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 P0 15 MR 14 TCD 13 TCU 12 PL 11 P2 10 P3 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC 1 P1 2 Q1 3 Q0 4 CPD 5 CPU 6 Q2 7 Q3 8 GND LOGIC SYMBOL 11 15 1 10 9 PIN NAMES LOADING (Note a) HIGH LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 (2.5) U.L. 5 4 CPU CPD PL P0 P1 P2 P3 TCU TCD CPU CPD MR PL Pn Qn TCD TCU Count Up Clock Pulse Input Count Down Clock Pulse Input Asynchronous Master Reset (Clear) Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Flip-Flop Outputs (Note b) Terminal Count Down (Borrow) Output (Note b) Terminal Count Up (Carry) Output (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. 10 U.L. 12 13 MR Q0 Q1 Q2 Q3 14 3 2 6 7 NOTES: a. 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 SN54/74LS192 * SN54/74LS193 STATE DIAGRAMS LS192 LOGIC EQUATIONS FOR TERMINAL COUNT TCU = Q0 Q3 CPU TCD = Q0 Q1 Q2 Q3 CPD 0 1 2 3 4 0 1 2 3 4 15 5 15 5 14 6 14 6 LS193 LOGIC EQUATIONS FOR TERMINAL COUNT 13 7 TCU = Q0 Q1 Q2 Q3 CPU TCD = Q0 Q1 Q2 Q3 CPD COUNT UP COUNT DOWN 13 7 12 11 10 9 8 12 11 10 9 8 LS192 LS193 LOGIC DIAGRAMS P0 PL (LOAD) CPU (UP COUNT) 11 5 12 15 1 P1 10 P2 9 P3 TCU (CARRY OUTPUT) SD T Q T SD Q T SD Q T SD Q CD Q CD Q CD Q CD Q 13 CPD (DOWN COUNT) MR (CLEAR) 4 14 3 2 6 7 TCD (BORROW OUTPUT) Q0 Q1 Q2 Q3 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS LS192 FAST AND LS TTL DATA 5-2 SN54/74LS192 * SN54/74LS193 LOGIC DIAGRAMS (continued) P0 PL (LOAD) CPU (UP COUNT) 11 5 12 15 1 P1 10 P2 9 P3 TCU (CARRY OUTPUT) SD T Q T SD Q T SD Q T SD Q CD Q CD Q CD Q CD Q 13 CPD (DOWN COUNT) MR (CLEAR) 4 14 3 2 6 7 TCD (BORROW OUTPUT) Q0 Q1 Q2 Q3 LS193 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FAST AND LS TTL DATA 5-3 SN54/74LS192 * SN54/74LS193 FUNCTIONAL DESCRIPTION The LS192 and LS193 are Asynchronously Presettable Decade and 4-Bit Binary Synchronous UP / DOWN (Reversable) Counters. The operating modes of the LS192 decade counter and the LS193 binary counter are identical, with the only difference being the count sequences as noted in the State Diagrams. Each circuit contains four master/slave flip-flops, with internal gating and steering logic to provide master reset, individual preset, count up and count down operations. Each flip-flop contains JK feedback from slave to master such that a LOW-to-HIGH transition on its T input causes the slave, and thus the Q output to change state. Synchronous switching, as opposed to ripple counting, is achieved by driving the steering gates of all stages from a common Count Up line and a common Count Down line, thereby causing all state changes to be initiated simultaneously. A LOW-to-HIGH transition on the Count Up input will advance the count by one; a similar transition on the Count Down input will decrease the count by one. While counting with one clock input, the other should be held HIGH. Otherwise, the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either Clock input is LOW. The Terminal Count Up (TCU) and Terminal Count Down (TCD) outputs are normally HIGH. When a circuit has reached the maximum count state (9 for the LS192, 15 for the LS193), the next HIGH-to-LOW transition of the Count Up Clock will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, thus effectively repeating the Count Up Clock, but delayed by two gate delays. Similarly, the TCD output will go LOW when the circuit is in the zero state and the Count Down Clock goes LOW. Since the TC outputs repeat the clock waveforms, they can be used as the clock input signals to the next higher order circuit in a multistage counter. Each circuit has an asynchronous parallel load capability permitting the counter to be preset. When the Parallel Load (PL) and the Master Reset (MR) inputs are LOW, information present on the Parallel Data inputs (P0, P3) is loaded into the counter and appears on the outputs regardless of the conditions of the clock inputs. A HIGH signal on the Master Reset input will disable the preset gates, override both Clock inputs, and latch each Q output in the LOW state. If one of the Clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that Clock will be interpreted as a legitimate signal and will be counted. MODE SELECT TABLE MR H L L L L PL X L H H H CPU X X H H CPD X X H H MODE Reset (Asyn.) Preset (Asyn.) No Change Count Up Count Down L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care = LOW-to-HIGH Clock Transition FAST AND LS TTL DATA 5-4 SN54/74LS192 * SN54/74LS193 GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 34 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol S bl fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter P Maximum Clock Frequency CPU Input to TCU Output CPD Input to TCD Output Clock to Q PL to Q MR Input to Any Output Min 25 Typ 32 17 18 16 15 27 30 24 25 23 26 24 24 24 38 47 40 40 35 Max Unit Ui MHz ns ns ns ns ns Test C di i T Conditions VCC = 5.0 V 50 CL = 15 pF FAST AND LS TTL DATA 5-5 SN54/74LS192 * SN54/74LS193 AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol S bl tW ts th trec Parameter P Any Pulse Width Data Setup Time Data Hold Time Recovery Time Min 20 20 5.0 40 Typ Max Unit Ui ns ns ns ns VCC = 5 0 V 5.0 Test C di i T Conditions DEFINITIONS OF TERMS SETUP TIME (ts) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the PL transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) is defined as the minimum time following the PL transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the PL transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs. FAST AND LS TTL DATA 5-6 SN54/74LS192 * SN54/74LS193 AC WAVEFORMS CPU or CPD 1.3 V tPHL tW tPLH 1.3 V Q 1.3 V 1.3 V Figure 1 CPU or CPD tPHL TCU or TCD 1.3 V tPLH 1.3 V Pn 1.3 V tPHL tPLH Qn 1.3 V NOTE: PL = LOW Figure 2 Figure 3 Pn tw PL 1.3 V tPLH Qn 1.3 V PL tW tPHL 1.3 V Q CPU or CPD tPHL 1.3 V 1.3 V 1.3 V trec Figure 4 Figure 5 Pn ts(H) PL 1.3 V th(H) ts(L) 1.3 V 1.3 V th(L) MR tW Q=P CPU or CPD tPHL Q 1.3 V 1.3 V trec 1.3 V Qn Q=P * The shaded areas indicate when the input is permitted * to change for predictable output performance Figure 6 Figure 7 FAST AND LS TTL DATA 5-7 |
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